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LTM4613
APPLICATIONS INFORMATION
A graphical representation of the aforementioned thermal
resistances is given in Figure 8. Blue resistances are
contained within the μModule package, whereas green
resistances are external to the μModule package.
As a practical matter, it should be clear to the reader that
no individual or sub group of the four thermal resistance
parameters defined by JESD51-12, or provided in the
Pin Configuration section, replicates or conveys normal
operating conditions of a μModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
of the package—as the standard defines for θ JCtop and
θ JCbottom , respectively. In practice, power loss is thermally
dissipated in both directions away from the package.
Granted, in the absence of a heat sink and airflow, the
majority of the heat flow is into the board.
Within a SIP (System-In-Package) module, be aware that
there are multiple power devices and components dissipat-
ing power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet:
1. Initially, FEA software is used to accurately build the
mechanical geometry of the μModule regulator and the
specified PCB with all of the correct material coefficients,
along with accurate power loss source definitions;
2. This model simulates a software-defined JEDEC envi-
ronment consistent with JSED51-9 to predict power
loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-
defined thermal resistance values;
3. The model and FEA software is used to evaluate the
μModule regulator with heat sinks and airflow;
4. Having solved for, and analyzed these thermal resistance
values and simulated various operating conditions in
the software model, a thorough laboratory evaluation
replicates the simulated conditions with thermocouples
within a controlled environment chamber while operat-
ing the device at the same power loss as that which
was simulated.
An outcome of this process and due diligence yields a set
of derating curves provided in other sections of this data
sheet. After these laboratory tests have been performed
and correlated to the μModule regulator model, the θ JB
and θ JA are summed together to correlate quite well with
the μModule regulator model, with no airflow or heat sink-
ing, in a properly defined chamber. This θ JB + θ JA value
is shown in the Pin Configuration section, and should
accurately equal the θ JA value in this section, because
approximately 100% of power loss flows from the junc-
tion through the board into ambient with no airflow or top
mounted heat sink.
The power loss curves in Figures 9 and 10 can be used
in coordination with the load current derating curves in
Figures 11 to 16 for calculating an approximate θ JA for
the module. Each figure has three curves that are taken
at three different airflow conditions. Graph designation
delineates between no heat sink, and a BGA heat sink. Each
of the load current derating curves will lower the maxi-
mum load current as a function of the increased ambient
temperature to keep the maximum junction temperature
of the power module at 125°C maximum. This will main-
tain the maximum operating temperature below 125°C.
Table?3 provides the approximate θ JA for Figures 11 to 16.
A complete explanation of the thermal characteristics is
provided in the thermal application note, AN110.
4613f
18
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